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Cadence Design Systems, Inc.: Media Advisory: Cadence Design Systems to Host Second Annual Silicon Valley Power Forward Low-Pow

^{Published on 2009-10-15 05:18:48 - Market Wire}
 

SAN JOSE, CA--(Marketwire - October 15, 2009) - Cadence Design Systems (NASDAQ: [ CDNS ])

 What: Power Forward Low-Power Design Summit When: 20 October 2009 8:30 am to 6:00 pm Where: Cadence Design Systems, Inc., 2655 Seely Ave., San Jose, CA 95134 Building 10 R&D Auditorium Press Registration: Contact Niki Tran at [ nikitran@cadence.com ] or (408) 428-5159 

Member companies of the Power Forward Initiative (PFI) and others will share their low-power design expertise, including best practices and proven capabilities that engineers can adopt to design energy-efficient wireless and wired electronics.

 -- Interact with presenters and panelists in sessions focusing on design experiences, low-power IP, and architectural design topics; -- Hear about ecosystem capabilities including advanced solutions that support a holistic low-power design methodology; -- Discuss emerging low-power design techniques and learn about the trends for future power efficient and 'green' technologies. 

Agenda:

 8:30 Registration and breakfast 9:00 Welcome and introduction 9:20 PFI members technical presentations GUC Si2 ARM Cadence 11:30 Industry Insight Panel Panelists: Wipro, Sonics, Cadence, AMD 12:00 Lunch 1:00 Technical presentations (Parallel tracks) (Design and verification) (Implementation and signoff) Calypto Virage Freescale Faraday Cadence Virage Mindtree Alchip Sonics Magma Q&A panel Q&A panel Panelists: Above member Panelists: Above member companies + NXP companies 4:15 Closing remarks/Raffle (Amazon Kindle, PFI Low-Power Guide) 4:30 Networking/drinks/hors d'oeuvres This schedule is subject to change 

About the Power Forward Initiative

The Power Forward Initiative, which has more than 40 member companies, is an industry initiative sponsored by Cadence Design Systems (NASDAQ: [ CDNS ]) and has the goal of enabling the design and production of more power-efficient electronic devices. The initiative includes companies representing a broad cross section of the design chain including system, semiconductor, foundry, IP, EDA, ASIC and design services companies. The Common Power Format (CPF) was contributed by Cadence to the Si2 Low Power Coalition in December 2006; CPF is now the most widely deployed low-power intent standard in the industry and available from Si2. The Initiative has also published A Practical Guide to Low-Power Design - User experience with CPF which is aimed at educating the broad design marketplace in utilizing advanced low-power design techniques. The Guide is available free of charge at [ www.powerforward.org ].