Science & Technology 
Science and Technology
Science and Technology 
Thu, July 16, 2009
Wed, July 15, 2009
Semitool: EMC3D Extends the Consortium Life Two Additional Years and Expands Goals for 300mm Thru-Silicon-Via Interconnect
KALISPELL, MT--(Marketwire - July 15, 2009) - Members of the international EMC3D semiconductor equipment and materials consortium today announced they will extend the life of the joint agreement to July 2011 from an original closing date of October 2009.
The initial goals of the consortium were to bring to market individual unit processes that can be quickly adopted into a volume production environment, and establish a basic understanding of the interactive relationship between process steps, all for a low overall Cost of Ownership (CoO) for 3D chip stacking.
The consortium originally identified a CoO target of $200usd per wafer for a fully processed die-to-wafer 3D stack on 300mm wafers. "Improvements of equipment efficiency, simplified process flow and reduced material expenses have been instrumental in lowering cost," said Paul Siblerud, EMC3D project director. "Today, fabs running iTSV can produce 3D-TSV devices at a total CoO of less than $150usd per wafer. Improved synchronization between the unit processes along with aggressive cost saving designs have been very successful at exceeding the consortium's original cost goals."
Sesh Ramaswami of Applied Materials said, "It has become clear that the larger diameter via-last pTSV used in DRAM, interposers and CIS devices have significantly different challenges than the smaller diameter high aspect ratio via-first iTSV structures. From etch and metallization, film stress management thru CMP and wafer bonding through debonding, these challenges require an integrated approach that EMC3D will focus on during this program extension."
"We are expanding our goal to include reliability improvements of both via-first (iTSV™) and via-last (pTSV™) processes," said Bioh Kim of EV Group. "Extending the roadmap to include a significantly reduced CoO to under $120usd per wafer will be a challenge, but one each member looks forward to working on."
About EMC3D
EMC3D (Semiconductor 3D Equipment and Materials Consortium) was created in September 2006 to develop and market wafer level 3D chip stacking technology by demonstrating a cost-effective, manufacturable, stackable TSV interconnection process for IC and MEMS/Sensor packaging. [ www.EMC3D.org ] or [ http://twitter.com/EMC3DTSV ]
*3D: three dimensional; MEMS: microelectromechanical systems; iTSV is interconnect Through-Silicon-Via; and pTSV is packaging Through-Silicon-Via or Via-First and Via-Last respectively.
Contacts for EMC3D Members include: Equipment Members: Applied Materials Inc., California, USA, (NASDAQ : [ AMAT ]); Sesh Ramaswami, Sr. Director, Strategy; Silicon Systems Group Technology: etching, dielectric and metal deposition, chemical-mechanical polishing, metrology, and inspection Datacon Technology GmbH, Austria; Christoph Scheiring, Director, Product Marketing Technology: Precision Diebonding & Sorting EV Group, Austria; Thorsten Matthias, Director of Technology, North America Technology: bonding, thin wafer handling, mask alignment lithography, conformal coat and develop SEMITOOL Inc., USA, (NASDAQ : [ SMTL ]); Paul Siblerud, V.P. ElectroChemical Deposition Technology: electroplating, metal/barrier etch, photoresist strip, wafer cleaning and thinning Wafer Reclaim Services, USA; Fred Schiele, V.P. & General Manager Technology: wafer service (reclaim and test wafers, wafer thinning, and thick-film SOI wafers) Materials Members: AZ Electronic Materials, USA; Aldo Orsi, Global Product Manager Technology: positive and negative acting photoresists Enthone (Cookson Electronics), USA; Yun Zhang, Global Business Director Technology: chemistry for plating, metal etch and pre-treatment The Dow company, USA; Bob Forman, Advanced Packaging Business Manager Technology: chemistry for lithography, plating, etching, dielectric formation, and bonding Brewer Science, Inc., USA; Mark Privett, Product Manager, Bonding Materials Technology: Anti-reflective coatings, specialty materials for compound semiconductor, optoelectronics, and MEMS applications. Spin coat, bake and develop processing equipment, planarization systems Technology Members: CEA-LETI, Grenoble, France; Mark Scannell, Microelectronics Program Manager Fraunhofer IZM, Germany; Jürgen Wolf, Group and Project Manager NXP; Dr. Fred Roozeboom, Technical Advisor KAIST (Korea Advanced Institute of Science and Technology), Korea; Dr. Kyung-Wook Paik, Professor SAIT (Samsung Advanced Institute of Technology), Korea; Dr. Yoon-Chul Sohn, Researcher TAMU (Texas A&M University), USA; Dr. Manuel Soriaga, Professor