Science & Technology
Science and Technology
Science and Technology
Mon, November 30, 2009 LatticeECP3 FPGA Family, ProcessorPM Power Management Device Honored by EDN China
HILLSBORO, OR--(Marketwire - November 30, 2009) - Lattice Semiconductor Corporation (
"Our mid-range ECP3 family has defined an entirely new class of FPGAs that delivers low cost and low power without sacrificing performance and features such as SERDES, large memory and high speed IO," said Douglas Hunter, Lattice Vice President of Corporate Marketing. "Power has become a major consideration in FPGA design, and it is especially gratifying that the ECP3 devices are the only low power, SERDES-capable FPGAs to receive the 2009 EDN China Innovation award.
"We are equally pleased to accept the EDN China Innovation award for our ProcessorPM power management device," Hunter continued, "a lower cost, more accurate, programmable, single chip solution that integrates the reset generation, watchdog timer and voltage supervision functions found in virtually every microprocessor or DSP design."
The LatticeECP3 family was recognized in the Programmable Logic category, and the ProcessorPM family in the Power Device category. The 2009 EDN China Innovation Product Awards were chosen by technology managers, researchers and an EDN China editor.
About the LatticeECP3 FPGA Family
The award-winning LatticeECP3 FPGA family is comprised of five devices that offer standards-compliant multi-protocol 3G SERDES, DDR1/2/3 memory interfaces for low cost FPGAs and high performance, cascadable DSP slices that are ideal for high performance RF, baseband and image signal processing. Toggling at 1Gbps, the LatticeECP3 FPGAs also feature the fastest LVDS I/O available in a mid-range FPGA family, as well as embedded memory of up to 6.8 Mbits. Logic density varies from 17K LUTs to 149K LUTs with up to 586 user I/O.
With these features, the LatticeECP3 FPGA family is ideally suited for deployment in high volume cost- and power-sensitive wireless infrastructure and wireline access equipment, as well as video and imaging, applications. For more information about the LatticeECP3 FPGA family, please visit [ www.latticesemi.com/products/fpga/ecp3 ]
About the ProcessorPM Power Management Device
The ProcessorPM device provides six programmable threshold comparators (accuracy -0.7 %) with individual glitch filters to monitor up to six supply rails without using external resistors and capacitors. The comparator outputs are connected to a 16 macrocell, ruggedized on-chip PLD (programmable logic device) that generates the reset and brownout signals by using simple logic equations. Four timers can be individually programmed from 32 microseconds to 2 seconds and used for implementing watchdog timers or for reset pulse stretching. Two digital inputs can be used for manual reset inputs or for monitoring other digital inputs such as Power Down or Disable Processor signals. For more information about the ProcessorPM device, please visit [ www.latticesemi.com/products/powermanager/processorpmpowr605 ]
About Lattice Semiconductor
Lattice is the source for innovative FPGA, PLD, programmable Power Management and Clock Management solutions. For more information, visit [ www.latticesemi.com ]
Lattice Semiconductor Corporation, Lattice (& design), L (& design), LatticeECP3, ProcessorPM and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries.
GENERAL NOTICE: Other product names used in this publication are for identification purposes only and may be trademarks of their respective holders.
