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Hitachi Achieves Test Compression Levels Four Years Ahead of Industry (ITRS) Roadmap by Leveraging Cadence OPMISR Compression T

^{Published on 2009-11-02 05:06:06 - Market Wire}
 

SAN JOSE, CA--(Marketwire - November 2, 2009) - Cadence Design Systems, Inc. (NASDAQ: [ CDNS ]), the leader in global electronic design innovation, has delivered advanced test compression and fault modeling technology to Hitachi Ltd., resulting in increased IC product quality and significant cost savings in manufacturing with DFT Architect and True Time ATPG.

The [ Cadence® Encounter® Test solution ] combines SDF-based dynamic test pattern generation, OPMISR compression technology, pattern-fault modeling, and diagnostics to achieve extremely accurate fault modeling to eliminate test escapes. The combination of Encounter Test solution and Hitachi's HBIST enabled over 99% AC fault coverage while achieving 1,100X compression.

The achievement allows Hitachi to manufacture LSIs to industries such as computers, communications, transportation, medical devices, and other infrastructure equipments, which demand the most rigorous testing and quality assurance. In addition, the technology enables faster yield ramps and more accurate and efficient vector sets than previous solutions, eliminating the need for time-consuming iterative debug and refinement loops to achieve high-quality test patterns.

"Hitachi has collaborated with Cadence to deliver an innovative next-generation solution that is driven by our goals of meeting the complexity of advanced, nanometer designs, while achieving significant reduction in test cost and higher test quality," said Dr. Nobuo Tamba, General Manager of the Design & Development Operation, Micro Device Division, Hitachi, Ltd. "The collaboration has delivered an unparalleled 1,100X compression rate, which not only meets our own challenging manufacturing demands, but also the quality demands of customers in markets where reliability is mission-critical."

"Cadence Encounter Test solutions operate at performance specs that are well ahead of industry requirements," said Sanjiv Taneja, vice president of Encounter Test at Cadence. "This reflects our continuing commitment to solve customer design and manufacturing test challenges, no matter how big or complex, with solutions that exceed expectations and improve cost-effectiveness."

Cadence will demonstrate both Encounter True-Time ATPG and Encounter Test compression technology at the International Test Conference (ITC) 2009, November 2-5, 2009.

About Cadence

Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at [ www.cadence.com ].

Cadence, the Cadence logo and Encounter are registered trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.