SMIC and Cadence Announce the Availability of 65-Nanometer Low Power Reference Flow 4.0
SAN JOSE, CA--(Marketwire - October 29, 2009) - Cadence Design Systems, Inc. (
"Power is now a critical design constraint, as important as timing and area from both a technology and cost standpoint," said Max Liu, vice president of the Design Services Center at SMIC. "The SMIC-Cadence Reference Flow 4.0 addresses the need for power-efficient design innovation with an advanced, automated low-power design capability."
Validation of the flow was accomplished through implementation of low-power chips utilizing SMIC's in-house-designed 65-nanometer libraries, including effective current source model (ECSM) standard cells, power management cells, PLLs, SRAMs and I/O libraries. Low-power technologies employed in the design include power gating and multi-supply/multi-voltage (MSMV) techniques to reduce leakage and dynamic power consumption.
"Power efficiency is a key requirement for many new semiconductors, yet designers sometimes think it's too new and therefore too risky," said Steve Carlson, vice president of product marketing at Cadence. "The Cadence Low-Power Solution provides a complete, silicon-validated front-to-back flow for designers targeting SMIC's 65-nanometer process technology, including functional and structural verification, while increasing productivity. It's fast, easy and proven."
The SMIC 65-nanometer low-power Reference Flow 4.0 includes the Cadence Low-Power Solution, with Encounter® Conformal® Low Power, Incisive® Enterprise Simulator, Encounter RTL Compiler, Encounter Digital Implementation System, [ Cadence QRC Extraction ], Encounter Timing System and Encounter Power System.
About SMIC
Semiconductor Manufacturing International Corporation ("SMIC") (
About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at [ www.cadence.com ].
Cadence, the Cadence logo, Incisive, Encounter and Conformal are registered trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.