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Cadence Design Systems, Inc.: Fuji Electric Device Achieves Significant Cost Reduction With Cadence Virtuoso Accelerated Parall

^{Published on 2009-09-28 09:27:23 - Market Wire}
 

SAN JOSE, CA--(Marketwire - September 28, 2009) - Cadence Design Systems, Inc. (NASDAQ: [ CDNS ]), the leader in global electronic design innovation, today announced that Fuji Electric Device Technology Co., Ltd. cut development costs by about a third by using the [ Cadence® Virtuoso® ] Accelerated Parallel Simulator. The company, a leader in power management ICs, credited the simulator with helping design teams boost the quality of their chips, and get them to market faster.

Fuji Electric Device Technology develops high-voltage and high-efficiency AC/DC IC for green IDC power management, communication and automotive markets. To verify a full-chip power system, a simulation technology with high performance and full SPICE accuracy was required.

"The Virtuoso Accelerated Parallel Simulator enabled our design teams to reduce the number of prototyping iterations, leading to a 30 percent reduction in our development costs," said Takashi Kobayashi, general manager, Semiconductor Device R&D Dept., Electron Device Laboratory, Semiconductors Group, Fuji Electric Device Technology Co., Ltd. "Using the Accelerated Parallel Simulator, we have reduced simulation time up to 75 percent for our full-chip designs without sacrificing any accuracy. As a result we are able to deliver high-quality devices and meet the market window."

"We're glad to see Fuji Electric Device Technology place its logo alongside the many other leading technology companies who have discovered the capabilities and benefits of the Virtuoso Accelerated Parallel Simulator for small to large pre layout and post layout designs," said Zhihong Lui, corporate vice president at Cadence. "The company's experience of quality improvements and faster time to market is wholly consistent with what we've been hearing from other companies as well."

Part of the Virtuoso Multi-mode Simulation, the Virtuoso Accelerated Parallel Simulator provides the next generation SPICE accurate simulation, with scalable performance and capacity, for a broad class of complex analog, RF and mixed-signal blocks and sub-systems with ten thousands of devices. It is tightly integrated with the Virtuoso custom design platform and provides all the transistor-level analysis capabilities as in Virtuoso Spectre Simulator. The proprietary full matrix-solving algorithm delivers unparalleled scalable multi-threading capability using modern multi-core machines.

About Cadence

Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at [ www.cadence.com ].

Cadence, Virtuoso and the Cadence logo are registered trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.